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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1992 copyright ? intel corporation, 1995 order number: 270640-004 80C187 80-bit math coprocessor y high performance 80-bit internal architecture y implements ansi/ieee standard 754- 1985 for binary floating-point arithmetic y upward object-code compatible from 8087 y fully compatible with 387dx and 387sx math coprocessors. implements all 387 architectural enhancements over 8087 y directly interfaces with 80c186 cpu y 80c186/80C187 provide a software/ binary compatible upgrade from 80186/82188/8087 systems y expands 80c186's data types to include 32-, 64-, 80-bit floating-point, 32-, 64-bit integers and 18-digit bcd operands y directly extends 80c186's instruction set to trigonometric, logarithmic, exponential, and arithmetic instructions for all data types y full-range transcendental operations for sine, cosine, tangent, arctangent, and logarithm y built-in exception handling y eight 80-bit numeric registers, usable as individually addressable general registers or as a register stack y available in 40-pin cerdip and 44-pin plcc package (see packaging outlines and dimensions, order y 231369) the intel 80C187 is a high-performance math coprocessor that extends the architecture of the 80c186 with floating-point, extended integer, and bcd data types. a computing system that includes the 80C187 fully conforms to the ieee floating-point standard. the 80C187 adds over seventy mnemonics to the instruction set of the 80c186, including support for arithmetic, logarithmic, exponential, and trigonometric mathematical operations. the 80C187 is implemented with 1.5 micron, high-speed chmos iii technology and packaged in both a 40-pin cerdip and a 44-pin plcc package. the 80C187 is upward object-code compatible from the 8087 math coprocessor and will execute code written for the 80387dx and 80387sx math coprocessors.
80C187 270640 1 figure 1. 80C187 block diagram 2
80C187 80C187 data registers 79 78 64 63 0 r0 sign exponent significand r1 r2 r3 r4 r5 r6 r7 15 0 15 0 control register instruction pointer status register data pointer tag word figure 2. register set functional description the 80C187 math coprocessor provides arithmetic instructions for a variety of numeric data types. it also executes numerous built-in transcendental functions (e.g. tangent, sine, cosine, and log func- tions). the 80C187 effectively extends the register and instruction set of the 80c186 cpu for existing data types and adds several new data types as well. figure 2 shows the additional registers visible to pro- grams in a system that includes the 80C187. essen- tially, the 80C187 can be treated as an additional resource or an extension to the cpu. the 80c186 cpu together with an 80C187 can be used as a sin- gle unified system. a 80c186 system that includes the 80C187 is com- pletely upward compatible with software for the 8086/8087. the 80C187 interfaces only with the 80c186 cpu. the interface hardware for the 80C187 is not imple- mented on the 80c188. programming interface the 80C187 adds to the cpu additional data types, registers, instructions, and interrupts specifically de- signed to facilitate high-speed numerics processing. all new instructions and data types are directly sup- ported by the assembler and compilers for high-level languages. the 80C187 also supports the full 80387dx instruction set. all communication between the cpu and the 80C187 is transparent to applications software. the cpu automatically controls the 80C187 whenever a numerics instruction is executed. all physical memo- ry and virtual memory of the cpu are available for storage of the instructions and operands of pro- grams that use the 80C187. all memory addressing modes are available for addressing numerics oper- ands. the end of this data sheet lists by class the instruc- tions that the 80C187 adds to the instruction set. note: the 80C187 math coprocessor is also referred to as a numeric processor extension (npx) in this document. data types table 1 lists the seven data types that the 80C187 supports and presents the format for each type. op- erands are stored in memory with the least signifi- cant digit at the lowest memory address. programs retrieve these values by generating the lowest ad- dress. for maximum system performance, all oper- ands should start at even physical-memory address- es; operands may begin at odd addresses, but will require extra memory cycles to access the entire op- erand. internally, the 80C187 holds all numbers in the ex- tended-precision real format. instructions that load operands from memory automatically convert oper- ands represented in memory as 16-, 32-, or 64-bit integers, 32- or 64-bit floating-point numbers, or 18- digit packed bcd numbers into extended-precision real format. instructions that store operands in mem- ory perform the inverse type conversion. 3
80C187 numeric operands a typical npx instruction accepts one or two oper- ands and produces one (or sometimes two) results. in two-operand instructions, one operand is the con- tents of an npx register, while the other may be a memory location. the operands of some instructions are predefined; for example, fsqrt always takes the square root of the number in the top stack ele- ment (refer to the section on data registers). register set figure 2 shows the 80C187 register set. when an 80C187 is present in a system, programmers may use these registers in addition to the registers nor- mally available on the cpu. data registers 80C187 computations use the extended-precision real data type. table 1. data type representation in memory 270640 2 notes: 1. s e sign bit (0 e positive, 1 e negative) 2. d n e decimal digit (two per byte) 3. x e bits have no significance; 80C187 ignores when loading, zeros when storing 4. u e position of implicit binary point 5. i e integer bit of significand; stored in temporary real, implicit in single and double precision 6. exponent bias (normalized values): single: 127 (7fh) double: 1023 (3ffh) extended real: 16383 (3fffh) 7. packed bcd: ( b 1) s (d 17 ...d 0 ) 8. real: ( b 1) s (2 e-bias )(f 0 ,f 1 ...) 4
80C187 the 80C187 register set can be accessed either as a stack, with instructions operating on the top one or two stack elements, or as individually addressable registers. the top field in the status word identifies the current top-of-stack register. a ``push'' operation decrements top by one and loads a value into the new top register. a ``pop'' operation stores the value from the current top register and then increments top by one. the 80C187 register stack grows ``down'' toward lower-addressed registers. instructions may address the data registers either implicitly or explicitly. many instructions operate on the register at the top of the stack. these instruc- tions implicitly address the register at which top points. other instructions allow the programmer to explicitly specify which register to use. this explicit addressing is also relative to top. tag word the tag word marks the content of each numeric data register, as figure 3 shows. each two-bit tag represents one of the eight data registers. the prin- cipal function of the tag word is to optimize the npx's performance and stack handling by making it possible to distinguish between empty and nonemp- ty register locations. it also enables exception han- dlers to identify special values (e.g. nans or denor- mals) in the contents of a stack location without the need to perform complex decoding of the actual data. status word the 16-bit status word (in the status register) shown in figure 4 reflects the overall state of the 80C187. it may be read and inspected by programs. bit 15, the b-bit (busy bit) is included for 8087 com- patibility only. it always has the same value as the es bit (bit 7 of the status word); it does not indicate the status of the busy output of 80C187. bits 13 11 (top) point to the 80C187 register that is the current top-of-stack. the four numeric condition code bits (c 3 c 0 ) are similar to the flags in a cpu; instructions that per- form arithmetic operations update these bits to re- flect the outcome. the effects of these instructions on the condition code are summarized in tables 2 through 5. bit 7 is the error summary (es) status bit. this bit is set if any unmasked exception bit is set; it is clear otherwise. if this bit is set, the error signal is as- serted. bit 6 is the stack flag (sf). this bit is used to distin- guish invalid operations due to stack overflow or un- derflow from other kinds of invalid operations. when sf is set, bit 9 (c 1 ) distinguishes between stack overflow (c 1 e 1) and underflow (c 1 e 0). figure 4 shows the six exception flags in bits 5 0 of the status word. bits 5 0 are set to indicate that the 80C187 has detected an exception while executing an instruction. a later section entitled ``exception handling'' explains how they are set and used. note that when a new value is loaded into the status word by the fldenv or frstor instruction, the value of es (bit 7) and its reflection in the b-bit (bit 15) are not derived from the values loaded from memory but rather are dependent upon the values of the exception flags (bits 5 0) in the status word and their corresponding masks in the control word. if es is set in such a case, the error output of the 80C187 is activated immediately. 15 0 tag (7) tag (6) tag (5) tag (4) tag (3) tag (2) tag (1) tag (0) note: the index i of tag(i) is not top-relative. a program typically uses the ``top'' field of status word to determine which tag(i) field refers to logical top of stack. tag values: 00 e valid 01 e zero 10 e qnan, snan, infinity, denormal and unsupported formats 11 e empty figure 3. tag word 5
80C187 270640 3 es is set if any unmasked exception bit is set; cleared otherwise. see table 2 for interpretation of condition code. top values: 000 e register 0 is top of stack 001 e register 1 is top of stack # # # 111 e register 7 is top of stack for definitions of exceptions, refer to the section entitled, ``exception handling'' figure 4. status word 6
80C187 control word the npx provides several processing options that are selected by loading a control word from memory into the control register. figure 5 shows the format and encoding of fields in the control word. table 2. condition code interpretation instruction c0(s) c3(z) c1(a) c2(c) fprem, fprem1 three least significant reduction (see table 3) bits of quotient 0 e complete q2 q0 q1 1 e incomplete or o/u fcom, fcomp, fcompp, ftst result of comparison zero or operand is not fucom, fucomp, (see table 4) o/u comparable (table 4) fucompp, ficom, ficomp fxam operand class sign operand class (see table 5) or o/u (table 5) fchs, fabs, fxch, fincstp, fdecstp, constant loads, undefined zero undefined fxtract, fld, or o/u fild, fbld, fstp (ext real) fist, fbstp, frndint, fst, fstp, fadd, fmul, undefined roundup undefined fdiv, fdivr, or o/u fsub, fsubr, fscale, fsqrt, fpatan, f2xm1, fyl2x, fyl2xp1 fptan, fsin, undefined roundup reduction fcos, fsincos or o/u ,0 e complete undefined 1 e incomplete if c2 e 1 fldenv, frstor each bit loaded from memory fldcw, fstenv, fstcw, fstsw, undefined fclex, finit, fsave o/u when both ie and sf bits of status word are set, indicating a stack exception, this bit distinguishes between stack overflow (c1 e 1) and underflow (c1 e 0). reduction if fprem or fprem1 produces a remainder that is less than the modulus, reduction is complete. when reduction is incomplete the value at the top of the stack is a partial remainder, which can be used as input to further reduction. for fptan, fsin, fcos, and fsincos, the reduction bit is set if the operand at the top of the stack is too large. in this case the original operand remains at the top of the stack. roundup when the pe bit of the status word is set, this bit indicates whether one was added to the least significant bit of the result during the last rounding. undefined do not rely on finding any specific value in these bits. 7
80C187 the low-order byte of this control word configures exception masking. bits 5 0 of the control word contain individual masks for each of the six excep- tions that the 80C187 recognizes. the high-order byte of the control word configures the 80C187 operating mode, including precision, rounding, and infinity control. # the ``infinity control bit'' (bit 12) is not meaningful to the 80C187, and programs must ignore its val- ue. to maintain compatibility with the 8087, this bit can be programmed; however, regardless of its value, the 80C187 always treats infinity in the affine sense ( b % k a % ). this bit is initialized to zero both after a hardware reset and after the finit instruction. # the rounding control (rc) bits (bits 11 10) pro- vide for directed rounding and true chop, as well as the unbiased round to nearest even mode specified in the ieee standard. rounding control affects only those instructions that perform rounding at the end of the operation (and thus can generate a precision exception); namely, fst, fstp, fist, all arithmetic instructions (ex- cept fprem, fprem1, fxtract, fabs, and fchs), and all transcendental instructions. # the precision control (pc) bits (bits 9 8) can be used to set the 80C187 internal operating preci- sion of the significand at less than the default of 64 bits (extended precision). this can be useful in providing compatibility with early generation arith- metic processors of smaller precision. pc affects only the instructions add, sub, div, mul, and sqrt. for all other instructions, either the preci- sion is determined by the opcode or extended precision is used. table 3. condition code interpretation after fprem and fprem1 instructions condition code interpretation after c2 c3 c1 c0 fprem and fprem1 incomplete reduction: 1 x x x further iteration required for complete reduction q1 q0 q2 q mod 8 000 0 0 1 0 1 complete reduction: 0 1 0 0 2 c0, c3, c1 contain three least 1 1 0 3 significant bits of quotient 001 4 011 5 101 6 111 7 table 4. condition code resulting from comparison order c3 c2 c0 top l operand 0 0 0 top k operand 0 0 1 top e operand 1 0 0 unordered 1 1 1 8
80C187 table 5. condition code defining operand class c3 c2 c1 c0 value at top 0000 a unsupported 0001 a nan 0010 b unsupported 0011 b nan 0100 a normal 0101 a infinity 0110 b normal 0111 b infinity 1000 a 0 1001 a empty 1010 b 0 1011 b empty 1100 a denormal 1111 b denormal instruction and data pointers because the npx operates in parallel with the cpu, any exceptions detected by the npx may be report- ed after the cpu has executed the esc instruction which caused it. to allow identification of the failing numerics instruction, the 80C187 contains registers that aid in diagnosis. these registers supply the op- code of the failing numerics instruction, the address of the instruction, and the address of its numerics memory operand (if appropriate). the instruction and data pointers are provided for user-written exception handlers. whenever the 80C187 executes a new esc instruction, it saves the address of the instruction (including any prefixes that may be present), the address of the operand (if present), and the opcode. the instruction and data pointers appear in the for- mat shown by figure 6. the esc instruction fldenv, fstenv, fsave and frstor are used to transfer these values between the registers and memory. note that the value of the data pointer is undefined if the prior esc instruction did not have a memory operand. interrupt description cpu interrupt 16 is used to report exceptional condi- tions while executing numeric programs. interrupt 16 indicates that the previous numerics instruction caused an unmasked exception. the address of the faulty instruction and the address of its operand are stored in the instruction pointer and data pointer reg- isters. only esc instructions can cause this inter- rupt. the cpu return address pushed onto the stack of the exception handler points to an esc instruction (including prefixes). this instruction can be restarted after clearing the exception condition in the npx. fninit, fnclex, fnstsw, fnstenv, and fnsave cannot cause this interrupt. exception handling the 80C187 detects six different exception condi- tions that can occur during instruction execution. ta- ble 6 lists the exception conditions in order of prece- dence, showing for each the cause and the default action taken by the 80C187 if the exception is masked by its corresponding mask bit in the control word. any exception that is not masked by the control word sets the corresponding exception flag of the status word, sets the es bit of the status word, and asserts the error signal. when the cpu attempts to execute another esc instruction, interrupt 16 oc- curs. the exception condition must be resolved via an interrupt service routine. the return address pushed onto the cpu stack upon entry to the serv- ice routine does not necessarily point to the failing instruction nor to the following instruction. the 80C187 saves the address of the floating-point in- struction that caused the exception and the address of any memory operand required by that instruction. if error trapping is required at the end of a series of numerics instructions (specifically, when the last esc instruction modifies memory data and that data is used in subsequent nonnumerics instructions), it is necessary to insert the fnop instruction to force the 80C187 to check its error input. 9
80C187 270640 4 precision control 00e 24 bits (single precision) 01e (reserved) 10e 53 bits (double precision) 11e 64 bits (extended precision) rounding control 00e round to nearest or even 01e round down (toward b % ) 10e round up (toward a % ) 11e chop (truncate toward zero) * the ``infinity control'' bit is not meaningful to the 80C187. to maintain compatibility with the 8087, this bit can be programmed; however, regardless of its value, the 80C187 treats infinity in the affine sense ( b % k a % ). figure 5. control word 15 7 0 control word a 0 status word a 2 tag word a 4 instruction pointer 15..0 a 6 ip 19..16 0 opcode 10..0 a 8 operand pointer 15..0 a a op 19..16 000000000000 a c figure 6. instruction and data pointer image in memory 10
80C187 table 6. exceptions exception cause default action (if exception is masked) invalid operation on a signalling nan, result is a quiet nan, operation unsupported format, indeterminate integer indefinite, or form (0 * % , 0/0), ( a % ) bcd indefinite a ( b % ), etc.), or stack overflow/underflow (sf is also set) denormalized at least one of the operands is the operand is normalized, operand denormalized, i.e. it has the smallest and normal processing exponent but a nonzero significand continues zero divisor the divisor is zero while the dividend result is % is a noninfinite, nonzero number overflow the result is too large in magnitude result is largest finite to fit in the specified format value or % underflow the true result is nonzero but too small result is denormalized to be represented in the specified format, and, or zero if underflow exception is masked, denormalization causes loss of accuracy inexact the true result is not exactly representable normal processing result in the specified format (e.g. 1/3); continues (precision) the result is rounded according to the rounding mode initialization after fninit or reset, the control word contains the value 037fh (all exceptions masked, precision control 64 bits, rounding to nearest) the same values as in an 8087 after reset. for compatibility with the 8087, the bit that used to indicate infinity control (bit 12) is set to zero; however, regardless of its setting, infinity is treated in the affine sense. after fninit or reset, the status word is initialized as follows: # all exceptions are set to zero. # stack top is zero, so that after the first push the stack top will be register seven (111b). # the condition code c 3 c 0 is undefined . # the b-bit is zero. the tag word contains ffffh (all stack locations are empty). 80c186/80C187 initialization software should exe- cute an fninit instruction (i.e. an finit without a preceding wait) after reset. the fninit is not strictly required for 80C187 software, but intel recommends its use to help ensure upward compati- bility with other processors. 8087 compatibility this section summarizes the differences between the 80C187 and the 8087. many changes have been designed into the 80C187 to directly support the ieee standard in hardware. these changes result in increased performance by elminating the need for software that supports the standard. general differences the 8087 instructions feni/fneni and fdisi/ fndisi perform no useful function in the 80C187 numeric processor extension. they do not alter the state of the 80C187 numeric processor extension. (they are treated similarly to fnop, except that error is not checked.) while 8086/8087 code containing these instructions can be executed on the 80c186/80C187, it is unlikely that the exception- handling routines containing these instructions will be completely portable to the 80C187 numeric proc- essor extension. the 80C187 differs from the 8087 with respect to instruction, data, and exception synchronization. ex- cept for the processor control instructions, all of the 80C187 numeric instructions are automatically syn- chronized by the 80c186 cpu. when necessary, the 11
80C187 80c186 automatically tests the busy line from the 80C187 numeric processor extension to ensure that the 80C187 numeric processor extension has com- pleted its previous instruction before executing the next esc instruction. no explicit wait instructions are required to assure this synchronization. for the 8087 used with 8086 and 8088 cpus, explicit waits are required before each numeric instruction to en- sure synchronization. although 8086/8087 pro- grams having explicit wait instructions will execute on the 80c186/80C187, these wait instructions are unnecessary. the 80C187 supports only affine closure for infinity arithmetic, not projective closure. operands for fscale and fpatan are no longer restricted in range (except for g % ); f2xm1 and fptan accept a wider range of operands. rounding control is in effect for fld constant . software cannot change entries of the tag word to values (other than empty) that differ from actual reg- ister contents. after reset, finit, and incomplete fprem, the 80C187 resets to zero the condition code bits c 3 c 0 of the status word. in conformance with the ieee standard, the 80C187 does not support the special data formats pseudozero, pseudo-nan, pseudoinfinity, and un- normal. the denormal exception has a different purpose on the 80C187. a system that uses the denormal-ex- ception handler solely to normalize the denormal op- erands, would better mask the denormal exception on the 80C187. the 80C187 automatically normal- izes denormal operands when the denormal excep- tion is masked. exceptions a number of differences exist due to changes in the ieee standard and to functional improvements to the architecture of the 80c186/80C187: 1. the 80c186/80C187 traps exceptions only on the next esc instruction; i.e. the 80c186 does not notice unmasked 80C187 exceptions on the 80c186 error input line until a later numerics instruction is executed. because the 80c186 does not sample error on wait and fwait instructions, programmers should place an fnop instruction at the end of a sequence of numerics instructions to force the 80c186 to sample its error input. 2. the 80C187 numeric processor extension sig- nals exceptions through a dedicated error line to the cpu. the 80C187 error signal does not pass through an interrupt controller (the 8087 int signal does). therefore, any interrupt-controller- oriented instructions in numerics exception han- dlers for the 8086/8087 should be deleted. 3. interrupt vector 16 must point to the numerics ex- ception handling routine. 4. the esc instruction address saved in the 80C187 numeric processor extension includes any lead- ing prefixes before the esc opcode. the corre- sponding address saved in the 8087 does not include leading prefixes. 5. when the overflow or underflow exception is masked, the 80C187 differs from the 8087 in rounding when overflow or underflow occurs. the 80C187 produces results that are consistent with the rounding mode. 6. when the underflow exception is masked, the 80C187 sets its underflow flag only if there is also a loss of accuracy during denormalization. 7. fewer invalid-operation exceptions due to denor- mal operands, because the instructions fsqrt, fdiv, fprem, and conversions to bcd or to inte- ger normalize denormal operands before pro- ceeding. 8. the fsqrt, fbstp, and fprem instructions may cause underflow, because they support de- normal operands. 9. the denormal exception can occur during the transcendental instructions and the fxtract in- struction. 10. the denormal exception no longer takes prece- dence over all other exceptions. 11. when the denormal exception is masked, the 80C187 automatically normalizes denormal op- erands. the 8087 performs unnormal arithmetic, which might produce an unnormal result. 12. when the operand is zero, the fxtract in- struction reports a zero-divide exception and leaves b % in st(1). 13. the status word has a new bit (sf) that signals when invalid-operation exceptions are due to stack underflow or overflow. 14. fld extended precision no longer reports denor- mal exceptions, because the instruction is not numeric. 15. fld single/double precision when the operand is denormal converts the number to extended precision and signals the denormalized oper- 12
80C187 and exception. when loading a signalling nan, fld single/double precision signals an invalid- operand exception. 16. the 80C187 only generates quiet nans (as on the 8087); however, the 80C187 distinguishes between quiet nans and signalling nans. sig- nalling nans trigger exceptions when they are used as operands; quiet nans do not (except for fcom, fist, and fbstp which also raise ie for quiet nans). 17. when stack overflow occurs during fptan and overflow is masked, both st(0) and st(1) con- tain quiet nans. the 8087 leaves the original operand in st(1) intact. 18. when the scaling factor is g % , the fscale (st(0), st(1) instruction behaves as follows (st(0) and st(1) contain the scaled and scaling operands respectively): # fscale (0, % ) generates the invalid opera- tion exception. # fscale (finite, b % ) generates zero with the same sign as the scaled operand. # fscale (finite, a % ) generates % with the same sign as the scaled operand. the 8087 returns zero in the first case and rais- es the invalid-operation exception in the other cases. 19. the 80C187 returns signed infinity/zero as the unmasked response to massive overflow/under- flow. the 8087 supports a limited range for the scaling factor; within this range either massive overflow/underflow do not occur or undefined results are produced. table 7. pin summary pin function active input/ name state output clk clock i ckm clocking mode i reset system reset high i pereq processor extension high o request busy busy status high o error error status low o d 15 d 0 data pins high i/o nprd numeric processor read low i npwr numeric processor write low i nps1 npx select y 1 low i nps2 npx select y 2 high i cmd0 command 0 high i cmd1 command 1 high i v cc system power i v ss system ground i 13
80C187 hardware interface in the following description of hardware interface, an overbar above a signal name indicates that the ac- tive or asserted state occurs when the signal is at a low voltage. when no overbar is present above the signal name, the signal is asserted when at the high voltage level. signal description in the following signal descriptions, the 80C187 pins are grouped by function as follows: 1. execution controle clk, ckm, reset 2. npx handshakee pereq, busy, error 3. bus interface pinse d 15 d 0 , npwr , nprd 4. chip/port selecte nps1 , nps2, cmd0, cmd1 5. power suppliese v cc ,v ss table 7 lists every pin by its identifier, gives a brief description of its function, and lists some of its char- acteristics. figure 7 shows the locations of pins on the cerdip package, while figure 8 shows the loca- tions of pins on the plcc package. table 8 helps to locate pin identifiers in figures 7 and 8. clock (clk) this input provides the basic timing for internal oper- ation. this pin does not require mos-level input; it will operate at either ttl or mos levels up to the maximum allowed frequency. a minimum frequency must be provided to keep the internal logic properly functioning. depending on the signal on ckm, the signal on clk can be divided by two to produce the internal clock signal (in which case clk may be up to 32 mhz in frequency), or can be used directly (in which case clk may be up to 12.5 mhz). clocking mode (ckm) this pin is a strapping option. when it is strapped to v cc (high), the clk input is used directly; when strapped to v ss (low), the clk input is divided by two to produce the internal clock signal. during the reset sequence, this input must be stable at least four internal clock cycles (i.e. clk clocks when ckm is high; 2 c clk clocks when ckm is low) before reset goes low. 270640 5 * n.c. e pin not connected figure 7. cerdip pin configuration 270640 6 * n.c. e pin not connected ** ``top view'' means as the package is seen from the component side of the board. figure 8. plcc pin configuration 14
80C187 table 8. plcc pin cross-reference pin name cerdip package plcc package busy 25 28 ckm 39 44 clk 32 36 cmd0 29 32 cmd1 31 35 d 0 23 26 d 1 22 25 d 2 21 24 d 3 20 22 d 4 19 21 d 5 18 20 d 6 17 19 d 7 16 18 d 8 15 17 d 9 14 16 d 10 12 14 d 11 11 13 d 12 89 d 13 78 d 14 67 d 15 55 error 26 29 no connect 2 6, 11, 23, 33, 40 nprd 27 30 nps1 34 38 nps2 33 37 npwr 28 31 pereq 24 27 reset 35 39 v cc 3, 9, 13, 37, 40 1, 3, 10, 15, 42 v ss 1, 4, 10, 30, 36, 38 2, 4, 12, 34, 41, 43 system reset (reset) a low to high transition on this pin causes the 80C187 to terminate its present activity and to enter a dormant state. reset must remain active (high) for at least four internal clock periods. (the relation of the internal clock period to clk depends on clkm; the internal clock may be different from that of the cpu.) note that the 80C187 is active internal- ly for 25 clock periods after the termination of the reset signal (the high to low transition of re- set); therefore, the first instruction should not be written to the 80C187 until 25 internal clocks after the falling edge of reset. table 9 shows the status of the output pins during the reset sequence. after a reset, all output pins return to their inactive states. table 9. output pin status during reset output value pin name during reset busy high error high pereq low d 15 d 0 tri-state off processor extension request (pereq) when active, this pin signals to the cpu that the 80C187 is ready for data transfer to/from its data fifo. when there are more than five data transfers, 15
80C187 pereq is deactivated after the first three transfers and subsequently after every four transfers. this sig- nal always goes inactive before busy goes inactive. busy status (busy) when active, this pin signals to the cpu that the 80C187 is currently executing an instruction. this pin is active high. it should be connected to the 80c186's test /busy pin. during the reset se- quence this pin is high. the 80c186 uses this high state to detect the presence of an 80C187. error status (error ) this pin reflects the es bit of the status register. when active, it indicates that an unmasked excep- tion has occurred. this signal can be changed to inactive state only by the following instructions (with- out a preceding wait): fninit, fnclex, fnstenv, fnsave, fldcw, fldenv, and frstor. this pin should be connected to the error pin of the cpu. error can change state only when busy is active. data pins (d 15 d 0 ) these bidirectional pins are used to transfer data and opcodes between the cpu and 80C187. they are normally connected directly to the correspond- ing cpu data pins. other buffers/drivers driving the local data bus must be disabled when the cpu reads from the npx. high state indicates a value of one. d 0 is the least significant data bit. numeric processor write (npwr ) a signal on this pin enables transfers of data from the cpu to the npx. this input is valid only when nps1 and nps2 are both active. numeric processor read (nprd ) a signal on this pin enables transfers of data from the npx to the cpu. this input is valid only when nps1 and nps2 are both active. numeric processor selects (nps1 and nps2) concurrent assertion of these signals indicates that the cpu is performing an escape instruction and en- ables the 80C187 to execute that instruction. no data transfer involving the 80C187 occurs unless the device is selected by these lines. command selects (cmd0 and cmd1) these pins along with the select pins allow the cpu to direct the operation of the 80C187. system power (v cc ) system power provides the a 5v g 10% dc supply input. all v cc pins should be tied together on the circuit board and local decoupling capacitors should be used between v cc and v ss . system ground (v ss ) all v ss pins should be tied together on the circuit board and local decoupling capacitors should be used between v cc and v ss . processor architecture as shown by the block diagram (figure 1), the 80C187 npx is internally divided into three sections: the bus control logic (bcl), the data interface and control unit, and the floating-point unit (fpu). the fpu (with the support of the control unit which con- tains the sequencer and other support units) exe- cutes all numerics instructions. the data interface and control unit is responsible for the data flow to and from the fpu and the control registers, for re- ceiving the instructions, decoding them, and se- quencing the microinstructions, and for handling some of the administrative instructions. the bcl is responsible for cpu bus tracking and interface. bus control logic the bcl communicates solely with the cpu using i/o bus cycles. the bcl appears to the cpu as a special peripheral device. it is special in two re- spects: the cpu initiates i/o automatically when it encounters esc instructions, and the cpu uses re- served i/o addresses to communicate with the bcl. the bcl does not communicate directly with memo- ry. the cpu performs all memory access, transfer- ring input operands from memory to the 80C187 and transferring outputs from the 80C187 to memory. a dedicated communication protocol makes possible high-speed transfer of opcodes and operands be- tween the cpu and 80C187. 16
80C187 table 10. bus cycles definition nps1 nps2 cmd0 cmd1 nprd npwr bus cycle type x 0 x x x x 80C187 not selected 1 x x x x x 80C187 not selected 0 1 0 0 1 0 opcode write to 80C187 0 1 0 0 0 1 cw or sw read from 80C187 0 1 1 0 0 1 read data from 80C187 0 1 1 0 1 0 write data to 80C187 0 1 0 1 1 0 write exception pointers 0 1 0 1 0 1 reserved 0 1 1 1 0 1 read opcode status 0 1 1 1 1 0 reserved data interface and control unit the data interface and control unit latches the data and, subject to bcl control, directs the data to the fifo or the instruction decoder. the instruction de- coder decodes the esc instructions sent to it by the cpu and generates controls that direct the data flow in the fifo. it also triggers the microinstruction se- quencer that controls execution of each instruction. if the esc instruction is finit, fclex, fstsw, fstsw ax, fstcw, fsetpm, or frstpm, the control executes it independently of the fpu and the sequencer. the data interface and control unit is the one that generates the busy, pereq, and error signals that synchronize 80C187 activities with the cpu. floating-point unit the fpu executes all instructions that involve the register stack, including arithmetic, logical, transcen- dental, constant, and data transfer instructions. the data path in the fpu is 84 bits wide (68 significant bits, 15 exponent bits, and a sign bit) which allows internal operand transfers to be performed at very high speeds. bus cycles the pins nps1 , nps2, cmd0, cmd1, nprd and npwr identify bus cycles for the npx. table 10 de- fines the types of 80C187 bus cycles. 80C187 addressing the nps1 , nps2, cmd0, and cmd1 signals allow the npx to identify which bus cycles are intended for the npx. the npx responds to i/o cycles when the i/o address is 00f8h, 00fah, 00fch, or 00feh. the correspondence betwen i/o addresses and control signals is defined by table 11. to guarantee correct operation of the npx, programs must not perform any i/o operations to these reserved port addresses. table 11. i/o address decoding i/o address 80C187 select and command inputs (hexadecimal) nps2 nps1 cmd1 cmd0 00f8 1 0 0 0 00fa 1 0 0 1 00fc 1 0 1 0 00fe 1 0 1 1 17
80C187 cpu/npx synchronization the pins busy, pereq, and error are used for various aspects of synchronization between the cpu and the npx. busy is used to synchronize instruction transfer from the cpu to the 80C187. when the 80C187 rec- ognizes an esc instruction, it asserts busy. for most esc instructions, the cpu waits for the 80C187 to deassert busy before sending the new opcode. the npx uses the pereq pin of the cpu to signal that the npx is ready for data transfer to or from its data fifo. the npx does not directly access mem- ory; rather, the cpu provides memory access serv- ices for the npx. once the cpu initiates an 80C187 instruction that has operands, the cpu waits for pereq signals that indicate when the 80C187 is ready for operand transfer. once all operands have been transferred (or if the instruction has no operands) the cpu con- tinues program execution while the 80C187 exe- cutes the esc instruction. in 8086/8087 systems, wait instructions are re- quired to achieve synchronization of both com- mands and operands. the 80C187, however, does not require wait instructions. the wait or fwait instruction commonly inserted by high-level compil- ers and assembly-language programmers for excep- tion synchronization is not treated as an instruction by the 80c186 and does not provide exception trap- ping. (refer to the section ``system configuration for 8087-compatible exception trapping''.) once it has started to execute a numerics instruction and has transferred the operands from the cpu, the 80C187 can process the instruction in parallel with and independent of the host cpu. when the npx detects an exception, it asserts the error signal, which causes a cpu interrupt. opcode interpretation the cpu and the npx use a bus protocol that adapts to the numerics opcode being executed. only the npx directly interprets the opcode. some of the results of this interpretation are relevant to the cpu. the npx records these results (opcode status information) in an internal 16-bit register. the 80c186 accesses this register only via reads from npx port 00feh. tables 10 and 11 define the signal combinations that correspond to each of the follow- ing steps. 1. the cpu writes the opcode to npx port 00f8h. this write can occur even when the npx is busy or is signalling an exception. the npx does not necessarily begin executing the opcode immedi- ately. 2. the cpu reads the opcode status information from npx port 00feh. 3. the cpu initiates subsequent bus cycles accord- ing to the opcode status information. the opcode status information specifies whether to wait until the npx is not busy, when to transfer exception pointers to port 00fch, when to read or write op- erands and results at port 00fah, etc. for most instructions, the npx does not start exe- cuting the previously transferred opcode until the cpu (guided by the opcode status information) first writes exception pointer information to port 00fch of the npx. this protocol is completely transparent to programmers. bus operation with respect to bus interface, the 80C187 is fully asynchronous with the cpu, even when it operates from the same clock source as the cpu. the cpu initiates a bus cycle for the npx by activating both nps1 and nps2, the npx select signals. during the clk period in which nps1 and nps2 are activated, the 80C187 also examines the nprd and nprw 18
80C187 input signals to determine whether the cycle is a read or a write cycle and examines the cmd0 and cmd1 inputs to determine whether an opcode, oper- and, or control/status register transfer is to occur. the 80C187 activates its busy output some time after the leading edge of the nprd or nprw signal. input and ouput data are referenced to the trailing edges of the nprd and nprw signals. the 80C187 activates the pereq signal when it is ready for data transfer. the 80C187 deactivates pereq automatically. system configuration the 80C187 can be connected to the 80c186 cpu as shown by figure 9. (refer to the 80c186 data sheet for an explanation of the 80c186's signals.) this interface has the following characteristics: # the 80C187's nps1 , error , pereq, and busy pins are connected directly to the corre- sponding pins of the 80c186. # the 80c186 pin mcs3 /nps is connected to nps1 ; nps2 is connected to v cc . note that if the 80c186 cpu's den signal is used to gate exter- nal data buffers, it must be combined with the nps signal to insure numeric accesses will not activate these buffers. # the nprd and nprw pins are connected to the rd and wr pins of the 80c186. # cmd1 and cmd0 come from the latched a 2 and a 1 of the 80c186, respectively. # the 80C187 busy output connects to the 80c186 test /busy input. during reset, the signal at the 80C187 busy output automatically programs the 80c186 to use the 80C187. # the 80C187 can use the clkout signal of the 80c186 to conserve board space when operating at 12.5 mhz or less. in this case, the 80C187 ckm input must be pulled high. for operation in excess of 12.5 mhz, a double-frequency external oscillator for clk input is needed. in this case, ckm must be pulled low. 270640 7 figure 9. 80c186/80C187 system configuration 19
80C187 system configuration for 80186/ 80187-compatible exception trapping when the 80C187 error output signal is connect- ed directly to the 80c186 error input, floating- point exceptions cause interrupt y 16. however, ex- isting software may be programmed to expect float- ing-point exceptions to be signalled over an external interrupt pin via an interrupt controller. for exception handling compatible with the 80186/ 82188/8087, the 80c186 can be wired to recognize exceptions through an external interrupt pin, as fig- ure 10 shows. (refer to the 80c186 data sheet for an explanation of the 80c186's signals.) with this arrangement, a flip-flop is needed to latch busy upon assertion of error . the latch can then be cleared during the exception-handler routine by forc- ing a pcs pin active. the latch must also be cleared at reset in order for the 80c186 to work with the 80C187. 270640 8 * for input clocking options, refer to figure 9. figure 10. system configuration for 8087-compatible exception trapping 20
80C187 electrical data absolute maximum ratings * case temperature under bias (t c )0 cto a 85 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 0.5v to v cc a 0.5v power dissipation1.5w power and frequency requirements the typical relationship between i cc and the fre- quency of operation f is as follows: i cc typ e 55 a 5 * f ma where f is in mhz. when the frequency is reduced below the minimum operating frequency specified in the ac characteris- tics table, the internal states of the 80C187 may be- come indeterminate. the 80C187 clock cannot be stopped; otherwise, i cc would increase significantly beyond what the equation above indicates. notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. dc characteristics t c e 0 cto a 85 c, v cc ea 5v g 10% symbol parameter min max units test conditions v il input low voltage b 0.5 a 0.8 v v ih input high voltage 2.0 v cc a 0.5 v v icl clock input low voltage b 0.5 a 0.8 v v ich clock input high voltage 2.0 v cc a 0.5 v v ol output low voltage 0.45 v i ol e 3.0 ma v oh output high voltage 2.4 v i oh eb 0.4 ma i cc power supply current 156 ma 16 mhz 135 ma 12.5 mhz i li input leakage current g 10 m a0v s v in s v cc i lo i/o leakage current g 10 m a 0.45v s v out s v cc b 0.45v c in input capacitance 10 pf f c e 1 mhz c o i/o or output capacitance 12 pf f c e 1 mhz c clk clock capacitance 20 pf f c e 1 mhz 21
80C187 ac characteristics t c e 0 cto a 85 c, v cc e 5v g 10% all timings are measured at 1.5v unless otherwise specified 12.5 mhz 16 mhz test symbol parameter min max min max conditions (ns) (ns) (ns) (ns) t dvwh (t6) data setup to npwr 43 33 t whdx (t7) data hold from npwr 14 14 t rlrh (t8) nprd active time 59 54 t wlwh (t9) npwr active time 59 54 t avwl (t10) command valid to npwr 00 t avrl (t11) command valid to nprd 00 t mhrl (t12) min delay from pereq active 40 30 to nprd active t whax (t18) command hold from npwr 12 8 t rhax (t19) command hold from nprd 12 8 t ivcl (t20) nprd , npwr , reset to 46 38 note 1 clk setup time t clih (t21) nprd , npwr , reset from 26 18 note 1 clk hold time t rscl (t24) reset to clk setup 21 19 note 1 t clrs (t25) reset from clk hold 14 9 note 1 t cmdi (t26) command inactive time write to write 69 59 read to read 69 59 read to write 69 59 write to read 69 59 note: 1. this is an asynchronous input. this specification is given for testing purposes only, to assure recognition at a specific clk edge. 22
80C187 timing responses all timings are measured at 1.5v unless otherwise specified 12.5 mhz 16 mhz test symbol parameter min max min max conditions (ns) (ns) (ns) (ns) t rhqz (t27) nprd inactive to data float * 18 18 note 2 t rlqv (t28) nprd active to data valid 50 45 note 3 t ilbh (t29) error active to busy inactive 104 104 note 4 t wlbv (t30) npwr active to busy active 80 60 note 4 t klml (t31) nprd or npwr active 80 60 note 5 to pereq inactive t rhqh (t32) data hold from nprd inactive 2 2 note 3 t rlbh (t33) reset inactive to busy inactive 80 60 notes: * the data float delay is not tested. 2. the float condition occurs when the measured output current is less than i ol on d 15 d 0 . 3. d 15 d 0 loading: c l e 100 pf. 4. busy loading: c l e 100 pf. 5. on last data transfer of numeric instruction. clock timings 12.5 mhz 16 mhz * test symbol parameter min max min max conditions (ns) (ns) (ns) (ns) t clcl (t1a) clk period ckm e 1 80 250 n/a n/a note 6 (t1b) ckm e 0 40 125 31.25 125 note 6 t clch (t2a) clk low time ckm e 1 35 n/a note 6 (t2b) ckm e 0 9 7 note 7 t chcl (t3a) clk high time ckm e 1 35 n/a note 6 (t3b) ckm e 0 13 9 note 8 t ch2ch1 (t4) 10 8 note 9 t ch1ch2 (t5) 10 8 note 10 notes: * 16 mhz operation is available only in divide-by-2 mode (ckm strapped low). 6. at 1.5v 7. at 0.8v 8. at 2.0v 9. ckm e 1: 3.7v to 0.8v at 16 mhz, 3.5v to 1.0v at 12.5 mhz 10. ckm e 1: 0.8v to 3.7v at 16 mhz, 1.0v to 3.5v at 12.5 mhz 23
80C187 ac drive and measurement pointseclk input 270640 9 ac setup, hold, and delay time measurementsegeneral 270640 10 ac test loading on outputs 270640 11 data transfer timing (initiated by cpu) 270640 12 24
80C187 data channel timing (initiated by 80C187) 270640 13 error output timing 270640 14 clk, reset timing (ckm e 1) 270640 15 25
80C187 clk, nprd , npwr timing (ckm e 1) 270640 16 clk, reset timing (ckm e 0) 270640 17 reset must meet timing shown to guarantee known phase of internal divide by 2 circuits. note: reset, npwr , nprd inputs are asynchronous to clk. timing requirements are given for testing purposes only, to assure recognition at a specific clk edge. clk, nprd , npwr timing (ckm e 0) 270640 18 reset, busy timing 270640 19 26
80C187 80C187 extensions to the cpu's instruction set instructions for the 80C187 assume one of the five forms shown in table 12. in all cases, instructions are at least two bytes long and begin with the bit pattern 11011b, which identifies the escape class of instruction. instructions that refer to memory oper- ands specify addresses using the cpu's addressing modes. mod (mode field) and r/m (register/memory spec- ifier) have the same interpretation as the corre- sponding fields of cpu instructions (refer to pro- grammer's reference manual for the cpu). the disp (displacement) is optionally present in instruc- tions that have mod and r/m fields. its presence depends on the values of mod and r/m, as for in- structions of the cpu. the instruction summaries that follow assume that the instruction has been prefetched, decoded, and is ready for execution; that bus cycles do not require wait states; that there are no local bus hold re- quests delaying processor access to the bus; and that no exceptions are detected during instruction execution. timings are given in internal 80C187 clocks and include the time for opcode and data transfer between the cpu and the npx. if the in- struction has mod and r/m fields that call for both base and index registers, add one clock. table 12. instruction formats instruction optional first byte second byte field 1 11011 opa 1 mod 1 opb r/m disp 2 11011 mf opa mod opb * r/m disp 3 11011 d p opa 1 1 opb * st (i) 4 11011 0 0 1 1 1 1 op 5 11011 0 1 1 1 1 1 op 1511 10 9 8 7 6 5 4 3 2 1 0 notes: op e instruction opcode, possibly split into two fields opa and opb mf e memory format 00e 32-bit real 01e 32-bit integer 10e 64-bit real 11e 16-bit integer d e destination 0e destination is st(0) 0e destination is st(i) r xor d e 0e destination (op) source r xor d e 1e source (op) destination * in fsub and fdiv, the low-order bit of opb is the r (reversed) bit p e pop 0e do not pop stack 1e pop stack after operation esc e 11011 st(i) e register stack element i 000 e stack top 001 e second stack element # # # 111 e eighth stack element 27
80C187 80C187 extensions to the 80c186 instruction set encoding clock count range instruction byte byte optional 32-bit 32-bit 64-bit 16-bit 0 1 bytes 2 3 real integer real integer data transfer fld e load a integer/real memory to st(0) esc mf 1 mod 000 r/m disp 40 65 72 59 67 71 long integer memory to st(0) esc 111 mod 101 r/m disp 90 101 extended real memory to st(0) esc 011 mod 101 r/m disp 74 bcd memory to st(0) esc 111 mod 100 r/m disp 296 305 st(i) to st(0) esc 001 11000 st(i) 16 fst e store st(0) to integer/real memory esc mf 1 mod 010 r/m disp 58 93 107 73 80 93 st(0) to st(i) esc 101 11010 st(i) 13 fstp e store and pop st(0) to integer/real memory esc mf 1 mod 011 r/m disp 58 93 107 73 80 93 st(0) to long integer memory esc 111 mod 111 r/m disp 116 133 st(0) to extended real esc 011 mod 111 r/m disp 83 st(0) to bcd memory esc 111 mod 110 r/m disp 542 564 st(0) to st(i) esc 101 11001 st (i) 14 fxch e exchange st(i) and st(0) esc 001 11001 st(i) 20 comparison fcom e compare integer/real memory to st(0) esc mf 0 mod 010 r/m disp 48 78 85 67 77 81 st(i) to st(0) esc 000 11010 st(i) 26 fcomp e compare and pop integer/real memory to st esc mf 0 mod 011 r/m disp 48 78 85 67 77 81 st(i) to st(0) esc 000 11011 st(i) 28 fcompp e compare and pop twice st(1) to st(0) esc 110 1101 1001 28 ftst e test st(0) esc 001 1110 0100 30 fucom e unordered compare esc 101 11100 st(i) 26 fucomp e unordered compare and pop esc 101 11101 st(i) 28 fucompp e unordered compare and pop twice esc 010 1110 1001 28 fxam e examine st(0) esc 001 11100101 32-40 constants fldz e load a 0.0 into st(0) esc 001 1110 1110 22 fld1 e load a 1.0 into st(0) esc 001 1110 1000 26 fldpi e load pi into st(0) esc 001 1110 1011 42 fldl2t e load log 2 (10) into st(0) esc 001 1110 1001 42 shaded areas indicate instructions not available in 8087. note: a. when loading single- or double-precision zero from memory, add 5 clocks. 28
80C187 80C187 extensions to the 80c186 instruction set (continued) encoding clock count range instruction byte byte optional 32-bit 32-bit 64-bit 16-bit 0 1 bytes 2 3 real integer real integer constants (continued) fldl2e e load log 2 (e) into st(0) esc 001 1110 1010 42 fldlg2 e load log 10 (2) into st(0) esc 001 1110 1100 43 fldln2 e load log e (2) into st(0) esc 001 1110 1101 43 arithmetic fadd e add integer/real memory with st(0) esc mf 0 mod 000 r/m disp 44 52 77 92 65 73 77 91 st(i) and st(0) es cdp0 11000 st(i) 25 33 b fsub e subtract integer/real memory with st(0) esc mf 0 mod 10 r r/m disp 44 52 77 92 65 73 77 91 c st(i) and st(0) es cdp0 1110 r r/m 28 36 d fmul e multiply integer/real memory with st(0) esc mf 0 mod 001 r/m disp 47 57 81 102 68 93 82 93 st(i) and st(0) es cdp0 1100 1 r/m 31 59 e fdiv e divide integer/real memory with st(0) esc mf 0 mod 11 r r/m disp 108 140 147 f 128 142 146 g st(i) and st(0) es cdp0 1111 r r/m 90 h fsqrt i e square root esc 001 1111 1010 124 131 fscale e scale st(0) by st(1) esc 001 1111 1101 69 88 fprem e partial remainder of st(0) d st(1) esc 001 1111 1000 76 157 fprem1 e partial remainder (ieee) esc 001 1111 0101 97 187 frndint e round st(0) to integer esc 001 1111 1100 68 82 fxtract e extract components of st(0) esc 001 1111 0100 72 78 fabs e absolute value of st(0) esc 001 1110 0001 24 fchs e change sign of st(0) esc 001 1110 0000 26 27 shaded areas indicate instructions not available in 8087. notes: b. add 3 clocks to the range when d e 1. c. add 1 clock to each range when r e 1. d. add 3 clocks to the range when d e 0. e. typical e 54 (when d e 0, 48 56, typical e 51). f. add 1 clock to the range when r e 1. g. 153 159 when r e 1. h. add 3 clocks to the range when d e 1. i. b 0 s st(0) s a % . 29
80C187 80C187 extensions to the 80c186 instruction set (continued) encoding instruction byte byte optional clock count range 0 1 bytes 2 3 transcendental fcos e cosine of st(0) esc 001 1111 1111 125 774 j fptan k e partial tangent of st(0) esc 001 1111 0010 193 499 j fpatan e partial arctangent esc 001 1111 0011 316 489 fsin e sine of st(0) esc 001 1111 1110 124 773 j fsincos e sine and cosine of st(0) esc 001 1111 1011 196 811 j f2xm1 l e 2 st(0) b 1 esc 001 1111 0000 213 478 fyl2x m e st(1) * log 2 (st(0)) esc 001 1111 0001 122 540 fyl2xp1 n e st(1) * log 2 (st(0) a 1.0) esc 001 1111 1001 259 549 processor control finit e initialize npx esc 011 1110 0011 35 fstsw ax e store status word esc 111 1110 0000 17 fldcw e load control word esc 001 mod 101 r/m disp 23 fstcw e store control word esc 001 mod 111 r/m disp 21 fstsw e store status word esc 101 mod 111 r/m disp 21 fclex e clear exceptions esc 011 1110 0010 13 fstenv e store environment esc 001 mod 110 r/m disp 146 fldenv e load environment esc 001 mod 100 r/m disp 113 fsave e save state esc 101 mod 110 r/m disp 550 frstor e restore state esc 101 mod 100 r/m disp 482 fincstp e increment stack pointer esc 001 1111 0111 23 fdecstp e decrement stack pointer esc 001 1111 0110 24 ffree e free st(i) esc 101 1100 0 st(i) 20 fnop e no operations esc 001 1101 0000 14 shaded areas indicate instructions not available in 8087. notes: j. these timings hold for operands in the range l x l k q /4. for operands not in this range, up to 78 clocks may be needed to reduce the operand. k. 0 s l st(0) l k 2 63 . l. b 1.0 s st(0) s 1.0. m. 0 s st(0) k % , b % k st(1) k a % . n. 0 s l st(0) l k (2 b s (2))/2, b % k st(1) k a % . data sheet revision review the following list represents the key differences between the -002 and the -001 version of the 80C187 data sheet. please review this summary carefully. 1. figure 10, titled ``system configuration for 8087ecompatible exception trapping'', was replaced with a revised schematic. the previous configuration was faulty. updated timing diagrams on data transfer tim- ing, error output, and reset/busy. 30

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